But what's the play here besides promoting indigenous development? Alone, these cores are not remarkable, and getting 64 of them fed constantly is only useful for long-running HPC workloads.
To me the most interesting thing here is the 'Hawk' interconnect that allows some of these dies to be replaced with custom processing units; hardware encode/decode blocks sn a common option in consumer devices today, but any custom block can be made for specialized workloads.
The 128MB L3 is actually off chip... it is made up of 8 "CMC" (Cache & Memory Chips) that combine DDR3 and 16MB of L3. Each "panel" of 8 cores is connected to a single CMC.
All I know is that will be extremely expensive and low yield, and as far as I know, they haven't shown any of these "CMC" chips.
120W for the base chip, and even more power for L3 and DRAM (plus them being off die) will make it even higher latency. This is pretty DOA in terms of being a real competitor against Intel.
Wow! I suppose when you have 64 cores to feed...
But what's the play here besides promoting indigenous development? Alone, these cores are not remarkable, and getting 64 of them fed constantly is only useful for long-running HPC workloads.
To me the most interesting thing here is the 'Hawk' interconnect that allows some of these dies to be replaced with custom processing units; hardware encode/decode blocks sn a common option in consumer devices today, but any custom block can be made for specialized workloads.