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Good point, so could we make it "just write back but don't evict", something like fsync() for memory...?


That works only for the CPU->device direction. For the device->CPU direction, you have to evict so the next load will get the data the device wrote.


It occurs to me that a better solution, rather than having the CPU know when something else is going to write to the memory, is to have the memory tell the CPU when something else wrote to it. That would take a whole new memory protocol, though, and a new generation of CPU chips to use it...


We used "Computer Organization and Design: the Hardware/Software Interface" (also Hennessy and Patterson) as our comp arch textbook.

I'd recommend it (any moderately recent version) for simply learning as well.

Learning the internals of everything between memory and functional CPU subunits is fun (and useful).

And the ideas don't change that quickly (e.g. the TLB and ROBs that were attacked here have been around for decades in similar form). There's only so many clever things you can do when a one bit buffer is expensive.


Which edition? I think we used the 3rd edition in our class 5 or so years ago. It would not be something I'd "recommend" but I haven't looked elsewhere ( just assuming there is something better out there)


I couldn't say. I do remember at the time searching for a few topics on the net -- and sadly it was one of those "black holes" where there simply isn't equivalent information out there.

I imagine there might be some stuff in research papers, but that seems like an even worse learning experience.

For example: https://www.google.com/search?q=branch+prediction+scoreboard...


If you are interested about this sort of thing, I suggest reading "Computer Architecture: A quantitative approach" by Hennessy and Patterson.




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