It's been a long time since anyone tried to actually ship a chip with different instruction set support enabled across its cores, but Intel has spent the past several years shipping consumer parts where they had to disable some features (AVX-512) on their P-cores to bring them down to the level of what their E-cores support, because they didn't plan ahead for doing a heterogeneous chip with those two microarchitectures. Toggling off some instructions in microcode for some cores is quite different from having two microarchitectures that are each designed to implement the same instruction set but with different performance and power characteristics.